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Features
* 16-Mbit (x16) Flash and 8-Mbit PSRAM * 2.7V to 3.3V Operating Voltage * Low Operating Power
- 27 mA Operating Current - 53 A Standby Current * Extended Temperature Range
Flash
* 2.7V to 3.3V Read/Write * Access Time - 70 ns * Sector Erase Architecture * *
- Thirty-one 32K Word (64K Byte) Sectors with Individual Write Lockout - Eight 4K Word (8K Byte) Sectors with Individual Write Lockout Fast Word Program Time - 12 s Suspend/Resume Feature for Erase and Program - Supports Reading and Programming from Any Sector by Suspending Erase of a Different Sector - Supports Reading Any Word by Suspending Programming of Any Other Word Low-power Operation - 12 mA Active - 13 A Standby Data Polling, Toggle Bit, Ready/Busy for End of Program Detection VPP Pin for Write Protection and Accelerated Program/Erase Operations RESET Input for Device Initialization Sector Lockdown Support Top/Bottom Boot Block Configuration 128-bit Protection Register Minimum 100,000 Erase Cycles
16-Mbit Flash + 8-Mbit PSRAM Stack Memory AT52BC1661A AT52BC1661AT Preliminary
* * * * * * * *
PSRAM
* * * * *
8-Mbit (512K x 16) 2.7V to 3.3V VCC Operating Voltage 70 ns Access Time Fully Static Operation and Tri-state Output ISB0 < 10 A when Deep Power-Down Device Number AT52BC1661A(T) Flash Configuration
16M (1M x 16)
PSRAM Configuration 8M (512K x 16)
Rev. 3455A-STKD-11/04
1
CBGA Top View
1 2 3 4 5 6 7 8 9 10 11 12
A
NC NC NC A11 A15 A14 A13 A12 GND NC NC NC
B
A16 A8 A10 A9 I/O15 PWE I/O14 I/O7
C
WE RDY BUSY I/O13 I/O6 I/O4 I/O5
D
PGND RESET I/O12 ZZ PVCC VCC
E
NC VPP A19 I/O11 I/O10 I/O2 I/O3
F
PLB PUB POE I/O9 I/O8 I/O0 I/O1
G
A18 A17 A7 A6 A3 A2 A1 PCS1
H
NC NC NC A5 A4 A0 CE GND OE NC NC NC
Pin Configurations
Pin Name
Function
A0 - A18, A19 CE OE/POE WE/PWE VCC VPP I/O0-I/O15 PCS1 RDY/BUSY PVCC GND/PGND PUB PLB NC RESET ZZ
Common Address Input for 8M PSRAM/Flash, Flash Address Input Flash Chip Enable Flash/PSRAM, Output Enable Flash/PSRAM, Write Enable Flash Power Supply Optional Flash Power Supply for Faster Program/Erase Operations Data Inputs/Outputs PSRAM Chip Select Flash Ready/Busy Output PSRAM Power Supply Flash/PSRAM GND PSRAM Upper Byte PSRAM Lower Byte No Connect Flash Reset Low-Power Modes
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AT52BC1661A(T) [Preliminary]
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AT52BC1661A(T) [Preliminary]
Description
The AT52BC1661A(T) combines a single 16-Mbit Flash and a 8-Mbit PSRAM: both of the devices are offered in a stacked 66-ball CBGA package. The devices operate at 2.7V to 3.3V in the extended temperature range.
Block Diagram
ADDRESS OE WE POE PWE
RESET CE FLASH RDY/BUSY PSRAM PCS1 ZZ PUB PLB
DATA
Absolute Maximum Ratings
Temperature under Bias................................... -25C to +85C Storage Temperature ..................................... -55C to +150C All Input Voltages except VPP (including NC Pins) with Respect to Ground .............................-0.2V to VCC + 0.3V Voltage on VPP with Respect to Ground ..................................-0.2V to + 12.5V All Output Voltages with Respect to Ground .............................-0.2V to VCC + 0.3V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC and AC Operating Range
AT52BC1661A(T)-70 Operating Temperature (Case) VCC Power Supply Extended -25C to 85C 2.7V to 3.3V
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16-Mbit Flash Memory Block Diagram
I/O0 - I/O15
OUTPUT BUFFER
INPUT BUFFER
OUTPUT MULTIPLEXER
A0 - A19
INPUT BUFFER
DATA REGISTER
IDENTIFIER REGISTER
STATUS REGISTER
COMMAND REGISTER
CE WE OE RESET
ADDRESS LATCH DATA COMPARATOR
RDY/BUSY WRITE STATE MACHINE
Y-DECODER
Y-GATING
PROGRAM/ERASE VOLTAGE SWITCH
VPP
VCC GND X-DECODER
MAIN MEMORY
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AT52BC1661A(T) [Preliminary]
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AT52BC1661A(T) [Preliminary]
16-Mbit Flash Description
The 16-Mbit Flash is organized as 1,048,576 words of 16 bits each. The x16 data appears on I/O0 - I/O15. The memory is divided into 39 sectors for erase operations. The device has CE and OE control signals to avoid any bus contention. This device can be read or reprogrammed using a single power supply, making it ideally suited for in-system programming. The device powers on in the read mode. Command sequences are used to place the device in other operation modes such as program and erase. The device has the capability to protect the data in any sector (see "Sector Lockdown" section). To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend feature. This feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the memory. The end of a program or an erase cycle is detected by the READY/BUSY pin, Data Polling or by the toggle bit. The VPP pin provides data protection. When the VPP input is below 0.4V, the program and erase functions are inhibited. When VPP is at 0.9V or above, normal program and erase operations can be performed. A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement of entering the three-byte program sequence is offered to further improve programming time. After entering the six-byte code, only single pulses on the write control lines are required for writing into the device. This mode (Single Pulse Word Program) is exited by powering down the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing it back to VCC. Erase, Erase Suspend/Resume and Program Suspend/Resume commands will not work while in this mode; if entered they will result in data being programmed into the device. It is not recommended that the six-byte code reside in the software of the final product but only exist in external programming code.
Device Operation
READ: The Flash is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dualline control gives designers flexibility in preventing bus contention. COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or standby mode, depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the "Command Definition in Hex" table on page 13 (I/O8 - I/O15 are don't care inputs for the command codes). The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high impedance state. When a high level is reasserted on the RESET pin, the device returns to the read or standby mode, depending upon the state of the control inputs.
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ERASURE: Before a word can be reprogrammed, it must be erased. The erased state of memory bits is a logical "1". The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase command. CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase software code. After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time to erase the chip is tEC. If the sector lockdown has been enabled, the chip erase will not erase the data in the sector that has been locked out; it will erase only the unprotected sectors. After the chip erase, the device will return to the read or standby mode. SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 39 sectors (SA0 - SA38) that can be individually erased. The Sector Erase command is a six-bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched on the rising edge of WE. The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. The maximum time to erase a sector is tSEC. When the sector programming lockdown feature is not enabled, the sector will erase (from the same Sector Erase command). An attempt to erase a sector that has been protected will result in the operation terminating immediately. WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logical "0") on a word-by-word basis. Programming is accomplished via the internal device command register and is a four-bus cycle operation. The device will automatically generate the required internal program pulses. Any commands written to the chip during the embedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data "0" cannot be programmed back to a "1"; only erase operations can convert "0"s to "1"s. Programming is completed after the specified tBP cycle time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a program cycle. If the erase/program status bit is a "1", the device was not able to verify that the erase or program operation was performed successfully. VPP PIN: The circuitry of the device is designed so that it cannot be programmed or erased if the VPP voltage is less that 0.4V. When VPP is at 0.9V or above, normal program and erase operations can be performed. The VPP pin cannot be left floating. PROGRAM/ERASE STATUS: The device provides several bits to determine the status of a program or erase operation: I/O2, I/O3, I/O5, I/O6 and I/O7. The "Status Bit Table" on page 12 and the following four sections describe the function of these bits. To provide greater flexibility for system designers, the Flash contains a programmable configuration register. The configuration register allows the user to specify the status bit operation. The configuration register can be set to one of two different values, "00" or "01". If the configuration register is set to "00", the part will automatically return to the read mode after a successful program or erase operation. If the configuration register is set to a "01", a Product ID Exit command must be given after a successful program or erase operation before the part will return to the read mode. It is important to note that whether the configuration register is set to a "00" or to a "01", any unsuccessful program or erase operation requires using the Product ID Exit command to return the device to read mode. The default value (after power-up) for the configuration register is "00". Using the four-bus cycle Set Configuration Register command as shown in the "Command Definition in Hex" table on page 13, the value of the configuration register can be changed. Voltages applied to the RESET pin will not alter the value of the configuration register. The value of the configuration register will affect the operation of the I/O7 status bit as described below.
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AT52BC1661A(T) [Preliminary]
DATA POLLING: The 16-Mbit Flash features Data Polling to indicate the end of a program cycle. If the status configuration register is set to a "00", during a program cycle an attempted read of the last word loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to read the device will give a "0" on I/O7. Once the program or erase cycle has completed, true data will be read from the device. Data Polling may begin at any time during the program cycle. Please see "Status Bit Table" on page 12 for more details. If the status bit configuration register is set to a "01", the I/O7 status bit will be low while the device is actively programming or erasing data. I/O7 will go high when the device has completed a program or erase operation. Once I/O7 has gone high, status information on the other pins can be checked. The Data Polling status bit must be used in conjunction with the erase/program and VPP status bit as shown in the algorithm in Figures 1 and 2 on page 10. TOGGLE BIT: In addition to Data Polling the device provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the memory will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. Please see "Status Bit Table" on page 12 for more details. The toggle bit status bit should be used in conjunction with the erase/program and VPP status bit as shown in the algorithm in Figures 3 and 4 on page 11. ERASE/PROGRAM STATUS BIT: The device offers a status bit on I/O5, which indicates whether the program or erase operation has exceeded a specified internal pulse count limit. If the status bit is a "1", the device is unable to verify that an erase or a word program operation has been successfully performed. If a program (Sector Erase) command is issued to a protected sector, the protected sector will not be programmed (erased). The device will go to a status read mode and the I/O5 status bit will be set high, indicating the program (erase) operation did not complete as requested. Once the erase/program status bit has been set to a "1", the system must write the Product ID Exit command to return to the read mode. The erase/program status bit is a "0" while the erase or program operation is still in progress. Please see "Status Bit Table" on page 12 for more details. V PP STATUS BIT: The device provides a status bit on I/O3, which provides information regarding the voltage level of the VPP pin. During a program or erase operation, if the voltage on the VPP pin is not high enough to perform the desired operation successfully, the I/O3 status bit will be a "1". Once the VPP status bit has been set to a "1", the system must write the Product ID Exit command to return to the read mode. On the other hand, if the voltage level is high enough to perform a program or erase operation successfully, the VPP status bit will output a "0". Please see "Status Bit Table" on page 12 for more details. SECTOR LOCKDOWN: Each sector has a programming lockdown feature. This feature prevents programming of data in the designated sectors once the feature has been enabled. These sectors can contain secure code that is used to bring up the system. Enabling the lockdown feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; any sector's usage as a write-protected region is optional to the user.
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At power-up or reset, all sectors are unlocked. To activate the lockdown for a specific sector, the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked down, the contents of the sector is read-only and cannot be erased or programmed. SECTOR LOCKDOWN DETECTION: A software method is available to determine if programming of a sector is locked down. When the device is in the software product identification mode (see "Software Product Identification Entry/Exit" sections on page 23), a read from address location 00002H within a sector will show if programming the sector is locked down. If the data on I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program lockdown feature has been enabled and the sector cannot be programmed. The software product identification exit code should be used to return to standard operation. SECTOR LOCKDOWN OVERRIDE: The only way to unlock a sector that is locked down is through reset or power-up cycles. After power-up or reset, the content of a sector that is locked down can be erased and reprogrammed. ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to interrupt a sector or chip erase operation and then program or read data from a different sector within the memory. After the Erase Suspend command is given, the device requires a maximum time of 15 s to suspend the erase operation. After the erase operation has been suspended, the system can then read data or program data to any other sector within the device. An address is not required during the Erase Suspend command. During a sector erase suspend, another sector cannot be erased. To resume the sector erase operation, the system must write the Erase Resume command. The Erase Resume command is a one-bus cycle command. The device also supports an erase suspend during a complete chip erase. While the chip erase is suspended, the user can read from any sector within the memory that is protected. The command sequence for a chip erase suspend and a sector erase suspend are the same. PROGRAM SUSPEND/PROGRAM RESUME: The Program Suspend command allows the system to interrupt a programming operation and then read data from a different word within the memory. After the Program Suspend command is given, the device requires a maximum of 20 s to suspend the programming operation. After the programming operation has been suspended, the system can then read data from any other word that is not contained in the sector in which the programming operation was suspended. An address is not required during the program suspend operation. To resume the programming operation, the system must write the Program Resume command. The program suspend and resume are one-bus cycle commands. The command sequence for the erase suspend and program suspend are the same, and the command sequence for the erase resume and program resume are the same. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see "Operating Modes" on page 16 (for hardware operation) or "Software Product Identification Entry/Exit" sections on page 23. The manufacturer and device codes are the same for both modes. 128-BIT PROTECTION REGISTER: The device contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number. The data in block B is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. To program block B in the protection register, the four-bus cycle Program Protection Register command must be used as shown in the "Command Definition in Hex" table on page 13. To lock out block B, the four-bus cycle Lock Protection Register command
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AT52BC1661A(T) [Preliminary]
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AT52BC1661A(T) [Preliminary]
must be used as shown in the "Command Definition in Hex" table. Data bit D1 must be zero during the fourth bus cycle. All other data bits during the fourth bus cycle are don't cares. To determine whether block B is locked out, the Product ID Entry command is given followed by a read operation from address 80H. If data bit D1 is zero, block B is locked. If data bit D1 is one, block B can be reprogrammed. Please see the "Flash Protection Register Addressing Table" on page 13 for the address locations in the protection register. To read the protection register, the Product ID Entry command is given followed by a normal read operation from an address within the protection register. After determining whether block B is protected or not, or reading the protection register, the Product ID Exit command must be given prior to performing any other operation. RDY/BUSY: For the 16-Mbit Flash, an open-drain READY/BUSY output pin provides another method of detecting the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. The open-drain connection allows for OR-tying of several devices to the same RDY/BUSY line. Please see "Status Bit Table" on page 12 for more details. HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against inadvertent programs to the device in the following ways: (a) VCC sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) VCC power-on delay: once VCC has reached the VCC sense level, the device will automatically time out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Program inhibit: VPP is less than VILPP. (e) VPP power-on delay: once VPP has reached 1.65V, program and erase operations are inhibited for 100 ns. INPUT LEVELS: While operating with a 2.7V to 3.3V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to VCC + 0.3V.
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Figure 1. Data Polling Algorithm (Configuration Register = 00)
Figure 2. Data Polling Algorithm (Configuration Register = 01)
START
START
Read I/O7 - I/O0
Read I/O7 - I/O0 Addr = VA
Read I/O7 - I/O0
YES I/O7 = Data?
Toggle Bit = Toggle? NO
NO
YES
NO
I/O3, I/O5 = 1?
NO
I/O3, I/O5 = 1?
YES Read I/O7 - I/O0 Addr = VA
YES Read I/O7 - I/O0 Twice
I/O7 = Data?
YES
Toggle Bit = Toggle? YES
NO
NO Program/Erase Operation Not Successful, Write Product ID Exit Command Program/Erase Operation Successful, Device in Read Mode
Note: Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. I/O7 should be rechecked even if I/O5 = "1" because I/O7 may change simultaneously with I/O5.
Program/Erase Operation Not Successful, Write Product ID Exit Command
Program/Erase Operation Successful, Write Product ID Exit Command
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address.
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AT52BC1661A(T) [Preliminary]
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AT52BC1661A(T) [Preliminary]
Figure 3. Toggle Bit Algorithm (Configuration Register = 00) Figure 4. Toggle Bit Algorithm (Configuration Register = 01)
START
START
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Toggle Bit = Toggle? YES NO I/O3, I/O5 = 1?
NO
Toggle Bit = Toggle? YES NO I/O3, I/O5 = 1?
NO
YES Read I/O7 - I/O0 Twice
YES Read I/O7 - I/O0 Twice
Toggle Bit = Toggle? YES Program/Erase Operation Not Successful, Write Product ID Exit Command
NO
Toggle Bit = Toggle? YES
NO
Program/Erase Operation Successful, Device in Read Mode
Program/Erase Operation Not Successful, Write Product ID Exit Command
Program/Erase Operation Successful, Write Product ID Exit Command
Note:
1. The system should recheck the toggle bit even if I/O5 = "1" because the toggle bit may stop toggling as I/O5 changes to "1".
Note:
1. The system should recheck the toggle bit even if I/O5 = "1" because the toggle bit may stop toggling as I/O5 changes to "1".
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Status Bit Table
Status Bit I/O7 Configuration Register Programming Erasing Erase Suspended & Read Erasing Sector Erase Suspended & Read Non-erasing Sector Erase Suspended & Program Non-erasing Sector Erase Suspended & Program Suspended and Reading from Nonsuspended Sectors Program Suspended & Read Programming Sector Program Suspended & Read Non-programming Sector Notes: 00 I/O7 0 1 DATA I/O7 I/O7 01 0 0 1 DATA 0 I/O6 00/01 TOGGLE TOGGLE 1 DATA TOGGLE I/O5(1) 00/01 0 0 0 DATA 0 I/O3(2) 00/01 0 0 0 DATA 0 I/O2 00/01 1 TOGGLE TOGGLE DATA TOGGLE RDY/BUSY 00/01 0 0 1 1 0
DATA
DATA
DATA
DATA
DATA
DATA
1
I/O7 DATA
1 DATA
1 DATA
0 DATA
0 DATA
TOGGLE DATA
1 1
1. I/O5 switches to a "1" when a program or an erase operation has exceeded the maximum time limits or when a program or sector erase operation is performed on a protected sector. 2. I/O3 switches to a "1" when the VPP level is not high enough to successfully perform program and erase operations.
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AT52BC1661A(T) [Preliminary]
Command Definition in Hex(1)
Command Sequence Read Chip Erase Sector Erase Word Program Dual Word Program(9) Enter Single Pulse Program Mode Single Pulse Word Program Sector Lockdown Erase/Program Suspend Erase/Program Resume Product ID Entry Product ID Exit(5) Product ID Exit(5) Program Protection Register Lock Protection Register - Block B Status of Block B Protection Set Configuration Register CFI Query Bus Cycles 1 6 6 4 5 6 1 6 1 1 3 3 1 4 4 4 4 1 1st Bus Cycle Addr Addr 555 555 555 555 555 Addr 555 XXX XXX 555 555 XXX 555 555 555 555 X55 Data DOUT AA AA AA AA AA DIN AA B0 30 AA AA F0(8) AA AA AA AA 98 AAA AAA AAA AAA 55 55 55 55 555 555 555 555 C0 C0 90 D0 Addr 080 80 XXX DIN X0 DOUT(6) 00/01(7) AAA AAA 55 55 555 555 90 F0(8) AAA(2) 55 555 80 555 AA AAA 55 SA(3)(4) 60 AAA(2) AAA AAA AAA AAA 55 55 55 55 55 555 555 555 555 555 80 80 A0 E0 80 555 555 Addr Addr1 555 AA AA DIN DIN1 AA Addr2 AAA DIN2 55 555 A0 AAA AAA 55 55 555 SA(3)(4) 10 30 2nd Bus Cycle Addr Data 3rd Bus Cycle Addr Data Addr 4th Bus Cycle Data 5th Bus Cycle Addr Data 6th Bus Cycle Addr Data
Notes:
1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). I/O15 - I/O8 are don't care. The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A19 through A11 are don't care. 2. Since A11 is a Don't Care, AAA can be replaced with 2AA. 3. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 14 - 16 for details). 4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power cycled. 5. Either one of the Product ID Exit commands can be used. 6. If data bit D1 is "0", block B is locked. If data bit D1 is "1", block B can be reprogrammed. 7. The default state (after power-up) of the configuration register is "00". 8. Bytes of data other than F0 may be used to exit the Product ID mode. However, it is recommended that F0 be used. 9. This fast programming option enables the user to program two words in parallel only when VPP = 12V. The Addresses, Addr1 and Addr2, of the two words, DIN1 and DIN2, must only differ in address A0. This command should be used during manufacturing purposes only.
Flash Protection Register Addressing Table
Word 0 1 2 3 4 5 6 7 Note: Use Factory Factory Factory Factory User User User User Block A A A A B B B B A7 1 1 1 1 1 1 1 1 A6 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 1 A2 0 0 0 1 1 1 1 0 A1 0 1 1 0 0 1 1 0 A0 1 0 1 0 1 0 1 0
All address lines not specified in the above table must be "0" when accessing the protection register, i.e., A19 - A8 = 0.
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Bottom Boot- Sector Address Table
x16 Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 Size (Words) 4K 4K 4K 4K 4K 4K 4K 4K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A19 - A0) 00000 - 00FFF 01000 - 01FFF 02000 - 02FFF 03000 - 03FFF 04000 - 04FFF 05000 - 05FFF 06000 - 06FFF 07000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF 20000 - 27FFF 28000 - 2FFFF 30000 - 37FFF 38000 - 3FFFF 40000 - 47FFF 48000 - 4FFFF 50000 - 57FFF 58000 - 5FFFF 60000 - 67FFF 68000 - 6FFFF 70000 - 77FFF 78000 - 7FFFF 80000 - 87FFF 88000 - 8FFFF 90000 - 97FFF 98000 - 9FFFF A0000 - A7FFF A8000 - AFFFF B0000 - B7FFF B8000 - BFFFF C0000 - C7FFF C8000 - CFFFF D0000 - D7FFF D8000 - DFFFF E0000 - E7FFF E8000 - EFFFF F0000 - F7FFF F8000 - FFFFF
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AT52BC1661A(T) [Preliminary]
Top Boot- Sector Address Table
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 4K 4K 4K 4K 4K 4K 4K 4K x16 Address Range (A19 - A0) 00000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF 20000 - 27FFF 28000 - 2FFFF 30000 - 37FFF 38000 - 3FFFF 40000 - 47FFF 48000 - 4FFFF 50000 - 57FFF 58000 - 5FFFF 60000 - 67FFF 68000 - 6FFFF 70000 - 77FFF 78000 - 7FFFF 80000 - 87FFF 88000 - 8FFFF 90000 - 97FFF 98000 - 9FFFF A0000 - A7FFF A8000 - AFFFF B0000 - B7FFF B8000 - BFFFF C0000 - C7FFF C8000 - CFFFF D0000 - D7FFF D8000 - DFFFF E0000 - E7FFF E8000 - EFFFF F0000 - F7FFF F8000 - F8FFF F9000 - F9FFF FA000 - FAFFF FB000 - FBFFF FC000 - FCFFF FD000 - FDFFF FE000 - FEFFF FF000 - FFFFF
15
3455A-STKD-11/04
DC and AC Operating Range
16-Mbit Flash-70 Operating Temperature (Case) VCC Power Supply Extended -25C to 85C 2.70V to 3.3V
Operating Modes
Mode Read Program/Erase(2) Standby/Program Inhibit CE VIL VIL VIH X Program Inhibit X X Output Disable Reset Product Identification Hardware VIL VIL VIH VIH A1 - A19 = VIL, A9 = VH(3), A0 = VIL A1 - A19 = VIL, A9 = VH(3), A0 = VIH A0 = VIL, A1 - A19 = VIL A0 = VIH, A1 - A19 = VIL Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code(4) X X OE VIL VIH X(1) X VIL X VIH X WE VIH VIL X VIH X X X X RESET VIH VIH VIH VIH VIH VIH VIH VIL VPP X VIHPP(6) X X X VILPP(7) X X X High-Z High-Z Ai Ai Ai X I/O DOUT DIN High-Z
Software(5)
VIH
Notes:
1. 2. 3. 4. 5. 6. 7.
X can be VIL or VIH. Refer to AC programming waveforms on page 21. VH = 12.0V 0.5V. Manufacturer Code: 001FH, Device Code: 00C0H - Bottom Boot, 00C2H, Top Boot. See details under "Software Product Identification Entry/Exit" on page 23. VIHPP (min) = 0.9V; VIHPP (max) = 3.6V. VILPP (max) = 0.4V.
16
AT52BC1661A(T) [Preliminary]
3455A-STKD-11/04
AT52BC1661A(T) [Preliminary]
DC Characteristics
Symbol ILI ILO ISB ICC (1) ICC1 IPP1 VIL VIH VOL1 VOL2 VOH1 VOH2 Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Active Read Current VCC Programming Current VPP Input Load Current Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage Output High Voltage Output High Voltage IOL = 2.1 mA IOL = 1.0 mA IOH = -400 A IOH = -100 A 2.4 2.5 2.0 0.45 0.20 Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCC - 0.3V to VCC f = 5 MHz; IOUT = 0 mA 13 12 Min Typ Max 2 10 25 25 40 5 0.6 Units A A A mA mA A V V V V V V
Note:
1. In the erase mode, ICC is 45 mA.
17
3455A-STKD-11/04
AC Read Characteristics
16-Mbit Flash-70 Symbol tRC tACC tCE(1) tOE(2) tDF(3)(4) tOH tRO Parameter Read Cycle Time Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever Occurred First RESET to Output Delay 0 0 0 100 Min 70 70 70 20 25 Max Units ns ns ns ns ns ns ns
AC Read Waveforms(1)(2)(3)(4)
tRC ADDRESS ADDRESS VALID
CE
tCE OE tOE tDF tACC tOH
RESET HIGH Z
tRO OUTPUT VALID
OUTPUT
Notes:
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested.
18
AT52BC1661A(T) [Preliminary]
3455A-STKD-11/04
AT52BC1661A(T) [Preliminary]
Input Test Waveforms and Measurement Level
tR, tF < 5 ns
Output Test Load
2.8V = V TM 1029 Ohm
1728 Ohm
CL
(1)
Pin Capacitance
f = 1 MHz, T = 25C(1)
Symbol CIN COUT Typ 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V
Note:
This parameter is characterized and is not 100% tested.
19
3455A-STKD-11/04
AC Word Load Characteristics
Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tWPH Parameter Address, OE Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Setup Time Data, OE Hold Time Write Pulse Width High Min 0 35 0 0 35 35 0 35 Max Units ns ns ns ns ns ns ns ns
AC Word Load Waveforms
WE Controlled
CE Controlled
20
AT52BC1661A(T) [Preliminary]
3455A-STKD-11/04
AT52BC1661A(T) [Preliminary]
Program Cycle Characteristics
Symbol tBP tBPD tAS tAH tDS tDH tWP tWPH tWC tRP tEC tSEC1 tSEC2 tES tPS Parameter Word Programming Time Word Programming Time in Dual Programming Mode Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Pulse Width Write Pulse Width High Write Cycle Time Reset Pulse Width Chip Erase Cycle Time Sector Erase Cycle Time (4K Word Sectors) Sector Erase Cycle Time (32K Word Sectors) Erase Suspend Time Program Suspend Time 0 35 35 0 35 35 70 500 25 3.0 5.0 15 10 Min Typ 12 6 Max 200 100 Units s s ns ns ns ns ns ns ns ns seconds seconds seconds s s
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
tWP tWPH tBP
WE
tAS tAH
555 AAA
tDH
555 ADDRESS 555
A0 - A19
tWC
tDS
AA 55 A0 INPUT DATA AA
DATA
Sector or Chip Erase Cycle Waveforms
OE
(1)
CE
tWP tWPH
WE
tAS tAH
555 AAA
tDH
555 555 AAA Note 2
A0-A19
tWC
tDS
AA 55 WORD 1 80 WORD 2 AA WORD 3 55 WORD 4 Note 3 WORD 5
tEC
DATA
WORD 0
Notes:
1. OE must be high only when WE and CE are both low. 2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased. (See note 3 under "Command Definitions in Hex" on page 13.) 3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
21
3455A-STKD-11/04
Data Polling Characteristics(1)
Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay
(2)
Min 10 10
Typ
Max
Units ns ns ns
Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in "AC Read Characteristics" on page 18.
0
ns
Data Polling Waveforms
WE CE OE tDH I/O7 A0-A19 An tOEH tOE HIGH Z An An An An tWR
Toggle Bit Characteristics(1)
Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay(2) OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in "AC Read Characteristics" on page 18. 50 0 Min 10 10 Typ Max Units ns ns ns ns ns
Toggle Bit Waveforms(1)(2)(3)
Notes:
1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary.
22
AT52BC1661A(T) [Preliminary]
3455A-STKD-11/04
AT52BC1661A(T) [Preliminary]
Software Product Identification Entry(1)
LOAD DATA AA TO ADDRESS 555
Sector Lockdown Enable Algorithm(1)
LOAD DATA AA TO ADDRESS 555
LOAD DATA 55 TO ADDRESS AAA
LOAD DATA 55 TO ADDRESS AAA
LOAD DATA 90 TO ADDRESS 555
LOAD DATA 80 TO ADDRESS 555
ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5)
LOAD DATA AA TO ADDRESS 555
Software Product Identification Exit(1)(6)
LOAD DATA AA TO ADDRESS 555 OR LOAD DATA F0 TO ANY ADDRESS
LOAD DATA 55 TO ADDRESS AAA
LOAD DATA 55 TO ADDRESS AAA
EXIT PRODUCT IDENTIFICATION MODE(4)
LOAD DATA 60 TO SECTOR ADDRESS
PAUSE 200 s(2)
LOAD DATA F0 TO ADDRESS 555
Notes:
EXIT PRODUCT IDENTIFICATION MODE(4)
1. Data Format: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex), and A11 - A19 (Don't Care). 2. Sector Lockdown feature enabled.
Notes:
1. Data Format: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex), and A11 - A19 (Don't Care). 2. A1 - A19 = VIL. Manufacturer Code is read for A0 = VIL; Device Code is read for A0 = VIH. 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 001FH(x16) Device Code: 00C0H (x16) - Bottom Boot; 00C2H (x16) - Top Boot. 6. Either one of the Product ID Exit commands can be used.
23
3455A-STKD-11/04
PSRAM Description
The Pseudo-SRAM (PSRAM) is an integrated memory based on a self-refresh DRAM array. The device is offered with a density of 8-Mbit organized as 512,288 words by 16 bits. It is designed to be identical in operation and interface to the standard 6T SRAMS. The device is designed for low standby, low operating current and includes a user configurable low-power mode. Two chip selects (PCS1 and ZZ) and an output enable (POE) is available to allow for easy memory expansion. Byte controls (PUB and PLB) allow the upper and lower bytes to be accessed independently and can also be used to deselect the device. The deep sleep mode reduces standby current drain while not retaining data in the array. * Fast Cycle Times
- TACC < 70 ns
PSRAM Features
* Very Low Standby Current
- ISB0 < 10 A @ 3.0V
* Very Low Operating Current
- 1.0 mA at 3.0 and 1 s (Typical)
* Memory Expansion with PCS1 and POE * TTL Compatible Three-state Output Driver
Functional Block Diagram
Clk Gen Precharge Circuit
PVCC PGND
Row Addresses
Row Select
Memory Array
I/O0 ~ I/O7
Data Cont
I/O Circuit Column select
I/O8 ~ I/O15
Data Cont
Data Cont
Column Addresses
PCS1 P OE PWE Control Logic PUB P LB ZZ
24
AT52BC1661A(T) [Preliminary]
3455A-STKD-11/04
AT52BC1661A(T) [Preliminary]
Functional Description
PCS1 H X(1) X(1) L H H H ZZ H L H H POE X
(1)
PWE X
(1)
PLB X
(1)
PUB X
(1)
I/O0 - 7 High-Z High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN
I/O8 - 15 High-Z High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN
Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
Power Standby Low-power Modes Standby Active Active Active Active Active Active Active Active
X(1) X(1) H
X(1) X(1) H
X(1) H L X
(1)
X(1) H X
(1)
L H L L H L L
L L L H L X(1) L H L Note: H H L
1. X means don't care (must be low or high state).
Recommended DC Operating Conditions(1)(2)
Item Supply Voltage Ground Input High Voltage Input Low Voltage Notes: 1. 2. 3. 4. Symbol PVCC PGND VIH VIL Min 2.7 0 0.8 PVCC -0.2
(4)
Max 3.3 0 PVCC + 0.2(3) 0.2 PVCC
Unit V V V V
TA = - 25C to 85C, otherwise specified. Overshoot and undershoot are sampled, not 100% tested. Overshoot: PVCC + 1.0V in case of pulse width < 20 ns. Undershoot: -1.0V in case of pulse width < 20 ns.
Capacitance(1) (f = 1 MHz, TA = 25C)
Item Input Capacitance I/O Capacitance Note: Symbol CIN CI/O Test Condition VIN = 0V VIN = 0V Min Max 8 8 Unit pF pF
1. Capacitance is sampled, not 100% tested.
25
3455A-STKD-11/04
DC and Operating Characteristics
Item Input Leakage Current Output Leakage Current Symbol ILI ILO ICC1 ICC2 Output Low Voltage Output High Voltage Standby Current (TTL) Standby Current (CMOS) Low Power Modes VOL VOH ISB ISB1 ISB0 Test Conditions VIN = PGND to PVCC PCS1 = VIH, ZZ = VIH, POE = VIH or PWE = VIL, VI/O = PGND to PVCC Cycle time = 1 s, 100% duty, I I/O = 0 mA, PCS1 < 0.2V, ZZ = VIH, VIN < 0.2V or VIN > PVCC - 0.2V Cycle time = Min, II/O = 0 mA, 100% duty, PCS1 = VIL, ZZ = VIH, VIN = VIL or VIH IOL = 0.5 mA IOH = -0.5 mA PCS1 = VIH, ZZ = VIH, other inputs = VIH or VIL PCS1 > PVCC -0.2V, ZZ > PVCC - 0.2V, other inputs = 0 ~ PVCC ZZ < 0.2V, other inputs = 0 ~ PVCC, no refresh (DPD) 0.8 PVCC 0.3 70 10 Min -1 -1 1 Typ Max 1 1 3 25 0.2 PVCC Unit A A mA mA V V mA A A
Average Operating Current
26
AT52BC1661A(T) [Preliminary]
3455A-STKD-11/04
AT52BC1661A(T) [Preliminary]
AC Characteristics (PVCC = 2.7V - 3.3V, TA = -25C to 85C)
Speed Bins 70 ns Parameter List Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output PUB, PLB Access Time Chip Select to Low-Z Output Read PUB, PLB Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output PUB, PLB Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write PUB, PLB Valid to End of Write Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z PCS1 High Pulse Width Symbol tRC tAA tCO tOE tBA tLZ tBLZ tOLZ tHZ tBHZ tOHZ tOH tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW tCP 10 10 5 0 0 0 5 70 60 0 60 60 50 0 0 20 0 5 10 5 40K 5 5 5 Min 70 Max 40K 70 70 25 70 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
27
3455A-STKD-11/04
Power Up Sequence Standby Mode State Machines
1. Apply Power. 2. Maintain stable power for a minimum of 200 s with PCS1 = VIH
Power On
PCS1 = VIH
Wait 200 s
Initial State
PCS1 = VIH, Z Z = VIH
PCS1 = VIL, Z Z = VIH PUB or/and PLB = VIL
Active Mode PCS1 = VlL ZZ = V IH PCS1 = VIH (or/and PUB = PLB = VIH) ZZ = VIH
PCS1 = VIH, ZZ = VIL
Standby Mode
Low Power (Data Invalid)
PCS1 = VIH, ZZ = VIL
Standby Mode Characteristics
Mode Standby Low Power Modes Memory Cell Data Valid Invalid Standby Current (A) 70 (ISB1) 10 (ISB0) Wait Time (s) 0 200
28
AT52BC1661A(T) [Preliminary]
3455A-STKD-11/04
AT52BC1661A(T) [Preliminary]
Read Cycle (1)
(Address Controlled, PCS1 = POE = VIL, ZZ = PWE = VIH, PUB or/and PLB = VIL)
Address
A H
Data Out
Previous Data Valid
Data Valid
Read Cycle (2)
(ZZ = PWE = VIH)
Address
A H
PCS1
A
PUB, PLB POE
Z
E
LZ
HZ
Data Out
High-Z
Data Valid
Notes:
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ (max) is less than tLZ (min) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC (tWC) for continuous periods > 40 s.
29
3455A-STKD-11/04
Write Cycle (1)
(PWE Controlled, ZZ = VIH)
C
Address
W
(2)
R (4)
PCS1
W W P (1)
PUB, PLB PWE Data In Data Out
S W High-Z HZ
Data Valid
W
High-Z
Data Undefined
Write Cycle (2)
(PCS1 Controlled, ZZ = VIH)
C
Address
S
PCS1
W (2) W
R (4)
PUB, PLB PWE
W P(1)
W
Dat a In Data Out
Data Valid
High-Z
High-Z
Write Cycle (3)
(PUB, PLB Controlled, ZZ = VIH)
C
Address
W (2)
R (4)
PCS1
W
PUB, PLB PWE
W S P (1)
W
Data In Data Out
Data Valid
High-Z
High-Z
Notes:
1. A write occurs during the overlap (tWP) of low PCS1 and PWE. A write begins when PCS1 goes low and PWE goes low with asserting PUB or PLB for single byte operation or simultaneously asserting PUB and PLB for double byte operation. A write ends at the earliest transition when PCS1 goes high and PWE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the PCS1 going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as PCS1 or PWE going high. 5. Do not access device with cycle timing shorter than tRC (tWC) for continuous periods > 40 s.
30
AT52BC1661A(T) [Preliminary]
3455A-STKD-11/04
AT52BC1661A(T) [Preliminary]
Deep Power-down Mode Entry/Exit
C
A4
(2)
R(4)
PCS1 PUB, PLB
W P (1)
PWE
ZWE tZZmin Next Cycle
ZZ
Register Write (DPD)
Deep Power Down Start
Deep Power Down Exit
Parameter tZZWE tR (Deep Power-down Mode Only) tZZmin
Description ZZ low to Write Enable Low Operation Recovery Time Low Power Mode Time
Min 0
Max 1 200
Units s s s
10
31
3455A-STKD-11/04
Ordering Information
tACC (ns) 70 70 Voltage Range 2.7V - 3.3V 2.7V - 3.3V Ordering Code AT52BC1661AT-70CI AT52BC1661A-70CI Flash Boot Block Top Bottom PSRAM Size 8-Mbit 8-Mbit Package 66C5 66C5 Operation Range Extended (-25 to 85C) Extended (-25 to 85C)
Package Type 66C5 66-ball, Plastic Chip-scale Ball Grid Array Package (CBGA)
32
AT52BC1661A(T) [Preliminary]
3455A-STKD-11/04
AT52BC1661A(T) [Preliminary]
Packaging Information
66C5 - CBGA
E
0.12 C C Seating Plane
Marked A1 Identifier D
Side View
Top View
A1 A
0.60 REF
E1 e A1 Ball Corner 1.20 REF
A B C D E F G H
D1 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL e
12 11 10 9 8 7 6 5 4 3 2 1
MIN 9.90 - 7.90 - - 0.25
NOM 10.00 8.80 8.00 5.60 - - 0.80 BSC
MAX 10.10 - 8.10 - 1.20 -
NOTE
E E1 D
Ob
Bottom View
D1 A A1 e Ob
-
0.40
-
09/19/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 66C5, 66-ball (12 x 8 Array), 10 x 8 x 1.2 mm Body, 0.8 mm Ball Pitch Chip-scale Ball Grid Array Package (CBGA) DRAWING NO. 66C5 REV. A
R
33
3455A-STKD-11/04
Atmel Corporation
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